1. Field of Invention
The present invention relates to a method of manufacturing integrated circuit. More particularly, the present invention relates to a method of manufacturing MOS device.
2. Description of Related Art
Metal silicide is a common material deposited over the gate terminals or interconnects of a semiconductor substrate for lowering contact resistance. In general, a metal silicide layer is formed by a chemical vapor deposition or a sputtering method. Thereafter, the silicide layer must undergo a high temperature annealing operation so that the lattice structure within the silicon nitride layer can be rearranged to eliminate various kinds of crystal defects. After awhile, defect-free grains gradually replace the original grains. This phenomenon is known as re-crystallization. The annealed crystalline metal silicide layer has a lower resistance than the amorphous silicide layer before the annealing operation. Since photolithographic operation is unnecessary in the process of forming a metal silicide layer, the metal silicide is formed by a self-aligned process. With ease of processing and low contact resistance, the self-aligned silicide process is now a common means of forming metallic contacts.
As the level of device integration increases, resistance in the source/drain regions of a MOS device will also increase. When the resistance in the source/drain regions has risen to a level almost equal to the MOS channel, a self-aligned suicide (also known as Salicide) layer must be formed over the source/drain regions. The self-aligned silicide layer not only can lower the sheet resistance in the source/drain regions, but integrity of the shallow junction between metal and the MOS can also be ensured as well.
Self-aligned silicide process is a common method of forming a metal silicide layer over a polysilicon gate electrode, thereby downward adjusting the value of resistance there. FIGS. 1A through 1C are cross-sectional views showing the progression of manufacturing steps in fabricating a MOS device according to the first conventional method. First, as shown in FIG. 1A, a semiconductor substrate 10 having device isolation structures 12 thereon is provided. The semiconductor substrate 10 further includes a patterned gate oxide layer 13, a polysilicon gate 14 and ion-doped source/drain regions 16.
Next, as shown in FIG. 1B, a sputtering method is used to deposit a titanium layer 18 over the semiconductor substrate 10 and over the polysilicon gate 14.
Next, a rapid thermal process (RTP) is carried out to form a metal suicide layer 20 over the polysilicon gate 14 and the source/drain regions 16. Subsequently, a wet etching method is employed to remove the unreacted and residual metal, thereby forming a structure as shown in FIG. 1C.
However, due to the miniaturization of polysilicon gate, contact stress between the polysilicon layer and the metal silicide layer will increase considerably. Moreover, the number of nucleation sites for the re-crystallization of metal silicide will be greatly reduced as well. The reduction of nucleation sites combined with an increase in contact stress will lead to a modification of the metal/silicon ratio within a metal suicide layer, for example the value of x in titanium silicide silicide TiSi.sub.X. Consequently, quality of the metal suicide film is poor and island shaped metal suicide layer structure will form. With a rough suicide layer as such, resistivity of the layer will increase and the operating speed of the gate terminal will be affected. For example, when a self-aligned silicide process is used to form a titanium silicide layer over the sub-quarter micron line (0.25 .mu.m) of a logic device, the uneven distribution of heat in subsequent high temperature annealing process will distort the metal polycide layer, and hence leading to a narrow line effect that may seriously affect the operating characteristics of the gate terminal.
FIGS. 2A and 2B are cross-sectional views showing the progression of manufacturing steps in fabricating a MOS device according to the second conventional method. First, as shown in FIG. 2A, a semiconductor substrate 100 having device isolation Structures 102 thereon is provided. Then, a gate oxide layer 103 and a polysilicon layer 104 are sequentially deposited over the substrate 100. Thereafter, a tungsten layer 106 is formed over the polysilicon layer 104.
Next, as shown in FIG. 2B, a metallic gate is patterned out. The metallic gate includes a gate oxide layer 103', a polysilicon layer 104' and a metallic layer 106'. Subsequently, ions are implanted into the substrate 100 on each side of the metallic gate structure to form source/drain regions 108. Because metal is generally more difficult to be removed than non-metal, the metal must be bombarded by ions in a plasma etching operation. However, plasma etching will also generate large amount of particles, and some of these particles may end up inside the substrate causing device contamination. Furthermore, during plasma etching, some of the ions may possess a sufficiently high energy level to cause plasma damages.
In addition, conventional method of using a photoresist layer to pattern the tungsten layer will lead to pattern misalignment. This is because the tungsten layer easily reflected back some of the light needed for exposing the photoresist layer, and hence the incoming light will be improperly focused. When the pattern is misaligned, critical dimensions (CDs) will be out of control. Therefore, subsequent processing operations will be affected.
In the manufacturing of highly integrated circuits, dual gate electrodes of the N-type and the P-type are employed. To lower the resistance of these gate terminals, a polycide structure is frequently formed. The n.sup.+ /p.sup.+ ions doped within the polysilicon layer in the gate region and the metal silicide layer on top, however, can easily cross-diffuse into each other through their junction. Hence, electrical properties of the electronic device may be affected.
In light of the foregoing, there is a need to provide an improved method of fabricating MOS device.